xyz軟體王

Cadence LDV V3.3 for Win32 (EDA 邏輯電路設計軟體)




破解說明:安裝說明請參見光碟\crack



軟體簡介:

Cadence LDV V3.3 for Win32 正式版


【軟體簡介】

Cadence LDV is Logic Design and Verification Bundle for EDA.
With Cadence ldv, EDA engineer can do simulation at behavior level
using Verilog-XL,NC-Verilog or NC-VHDL. You can browse your resource,
domostrate and compare waves quickly and browse signal stream.
Also, there are code management tools like VeriSure and VHDL Cover
and so on which can be used to analyze result of simulation.
Then u can also do simulation at gate level using Buldgates.
Verifault XL,another tool in the Bundle,can be used to dofault
analyzation.

Notes: This is windows version 3.3, Cadence has removed many function
from the bundle. It only includes SimVision and Verilog-XL. Bundle with
full function can be found in unix version. So pls waiting for our
Linux/Sun rls.;-)